有幸参与英文

i hope i would have a chance to take part in it.

If I am fortunate enough to participate it'd please me a lot.If I'm lucky enough to be part of it, it'd tickle me pink. （俚）

it is only a great honour to take part in an Olympic Game to people who are athletics

I hope I stay fortunate to be able to participate in all the time.

3 familiar with the mainstream FPGA and CPLD's internal structure, logic familiar with the development of the whole process, there is a high low-end FPGA chips use a variety of experiences, good Linux environment, the logic simulation and verification. And very good at hardware debugger can be a very good use of Candence (Allegro) and Protel (AD6), and other software. In the hierarchical image processing, high-speed IO, Memory control, DDS, LCD display, and so on have more experience in the design. And a certain degree of DSP development of the ability to drive the bottom. Work experience: In October 2005 to January 2006: Tianjin Freescale Semiconductor internship, is mainly responsible for testing the chip production line management and improve chip yield. And in practice have been outstanding during the medal intern. In March 2006 to September 2008: Beijing RIGOL Technology Co., Ltd. (RIGOL), the logic of Engineers office. During the on-the-job companies have participated in a number of research and development projects. The main 5 are as follows: 1. Digital signal generator project: the project to meet the special needs of the market in order to FPGA + SRAM-based architecture, 16 analog and 16 digital output, output SPI, I2C, RS232, PO, LIN and other figures, the frequency Ranging from 0 ~ 120MHz range, and has triggered a variety of output. The product from a hardware engineer and I together, from the initial needs analysis, detailed design, the latter part of the hardware debugger, production tracking, maintenance and upgrade to, and take part in the entire process. 2. Function Generator: the impact of the project to low-end market, by DSP + SDRAM + FPGA + CPLD, such as chips for the digital part of the main framework. Unlike most similar to the signal generator, which can output signals and basic signal modulation, the frequency of 0 ~ 25MHz. The effort by the five-member, I am responsible for the FPGA 80% of the products, including DDS control, modulation, and EBIU of DSP Communications, AD and DA control of the content, and so on. The integrity of the products involved in the research and development, production, listing the various stages. The company has created a handsome gains. 3. General Instrument display card: the design can be transferred to the company on a variety of instruments common graphics cards, in order to escape the heavy DSP image processing tasks. Universal card consists of three parts, FPGA + memory + LCD. I completed an independent project, the company is the sole developer of graphics cards. Graphics features include support for multiple layers of any size, anywhere and by the logic of superposition, and support for transparent color transparency settings, support for the Gamma Correction, or SDRAM support DDR2 memory to do with as much as 90% of the memory bandwidth utilization Rate. Support for SPI, PPI, EBIU such as the control interface, support for the yuan too, Kyocera, the Friends of the up, Sharp, Toshiba and other LCD screens. And the graphics have been CycloneII, StratixII, Spartan3a, V5 and other FPGA to achieve. And is widely used in the company's listed instruments. 4. Four-channel oscilloscope: the company to open up the market's first four-channel products. As part of the project team members, I assumed 40% of logic, including the CPLD control, FGPA active configuration, FPGA configuration encryption, FPGA and DSP communications, as well as DDR2 and so on the drive. It was also responsible for the design of all the underlying drivers of the DSP. The integrity of the products involved in the research and development of the whole process. 5. High-end oscilloscope project: The project is the introduction of high-end products, of which I was privileged to participate and be responsible for the completion of the CPLD control, 666M high-speed DDR2 interface, 1G high-speed serial communication (SERDES), 1.2G sampling AD data processing, waveform 90 Degree rotation, linear FFT computation, Pattern trigger, SPI protocol triggering and so on the logic of the task. The product's launch, a great deal of solid RIGOL measured in the domestic industry. Another: on-the-job, set up a dedicated FPGA simulation servers, the company increased the efficiency of the logic of staff collaboration, as a server and has been rooter, to help administrators to configure, manage CVS part of the logic of the code and submit changes. Has access to on-the-job during the team's outstanding Award, outstanding individual award, outstanding mentor award.本人急于赶时间，翻译草率，敬请谅解